This patent application is being filed concurrently with U.S. patent application Ser. No. 08/828,977, entitled "Amplifier for Use in Analog-to-Digital Signal Conversion," by Krishnaswamy Nagaraj (Attorney Docket No. "Nagaraj 16"), assigned to the same assignee and herein incorporated by reference.
1. Field of the Invention
The present invention is related to electrical circuits, and, in particular, to pipelined analog-to-digital converters.
2. Description of the Related Art
Pipelined analog-to-digital (A/D) converters are very commonly used in high-speed data converters. For example, a switched-capacitor algorithmic pipelined A/D converter is described in Lewis et al., "A 10-b 20-Msample/s Analog-to-Digital Converter," IEEE Journal of Solid-State Circuits, Vol. 27, No. 3, pp. 351-358, March 1992, the teachings of which are incorporated herein by reference. Such a converter employs a pipeline of N-1 stages for an N-bit converter, where each stage comprises an analog arithmetic unit followed by a two-level decision circuit and the analog arithmetic unit operation is performed by using a switched-capacitor network and an operational amplifier. The first stage accepts the analog input and produces a pair of decision bits (containing the equivalent of 1.5 binary bits of information) and an analog residue. These are passed on to the second stage, which treats the analog residue as its input and produces another 1.5 bits of information, as well as a new analog residue. This process continues until the residue reaches the last stage. The decision bits from all the stages represent a total of 1.5(N-1) bits of information. This means that redundancy exists within the bits of information. These are processed by a digital correction block that removes the redundancy and produces the final N-bit output. Any decision errors are corrected in this process.
Nagaraj, "Efficient Circuit Configurations For Algorithmic Analog-To-Digital Converters," IEEE Transactions On Circuits Systems-II: Analog and Digital Signal Processing, Vol. 40, No. 2, December, 1993, pp. 777-785 ("the Nagaraj article"), herein incorporated by reference, describes an A/D converter in which each amplifier is time-shared between two stages of the A/D converter, thereby reducing the total number of amplifiers used in such an A/D converter by a factor of two. For example, for a 10-bit pipelined A/D converter, five amplifiers are employed using the technique described in the Nagaraj article.
Despite the time-sharing technique for reducing the number of amplifiers, it is nonetheless desirable to continue to come up with approaches in which the number of amplifiers for an A/D converter may be further reduced. This is largely because such amplifiers typically employ significant chip area (for solid-state implementations) and consume significant amounts of power, and therefore increase the cost of the A/D converter. Thus, a need exists for other techniques for reducing the number of amplifiers employed in an A/D converter, such as a pipelined A/D converter, without reducing the number of bits the A/D converter can process.
Further aspects and advantages of this invention will become apparent from the detailed description which follows.